Shallow trench isolation (STI) technology is generally used to insulate adjacent NMOS and PMOS devices in the formation of complementary metal-oxide semiconductor (CMOS) devices.
As described in U.S. Pat. No. 7,436,030, with the dimension of semiconductor device continuously scaling down, STI becomes a preferable electrical isolation method for CMOS devices. This is because STI stress can introduce strain of the channel, which will improve the whole performance of the semiconductor device. However, as known for those skilled in the art, for CMOS devices, when STI stress improves the performance of one type of MOS transistors, e.g. NMOS transistors, it lowers the performance of the other type of MOS transistors, e.g. PMOS transistors. For instance, STI tensile stress can improve the driving current of NMOS transistors by increasing electron mobility, however, at the same time, decrease carrier mobility, and thus reduce the driving current of the neighboring PMOS transistors.
Therefore, a new STI process and a new corresponding semiconductor device is needed to solve the problems caused by the traditional STI process, so that the stress provided by the STI can be fully used in MOS transistors.